Before describing the present invention, a conventional semiconductor test apparatus is explained with reference to FIG. 4 to make it easier to understand the present invention.
As shown in FIG. 4, a semiconductor test apparatus 100 generally comprises a period generator 400, a pattern generator 300, a timing generator 200, a waveform formatter 500 and a logical comparison circuit 600.
The period generator 400 outputs period data on the basis of an input reference clock. The period data is sent to the pattern generator 300 and also sent to the timing generator 200 as a Rate signal (see FIG. 7). The period generator 400 also generates an address for saving data in memories 220, 230 in the timing generator 200 described later (see FIGS. 5, 7).
The pattern generator 300 outputs a test pattern signal and an expected value pattern signal on the basis of the period data. The test pattern signal is sent to the timing generator 200, and the expected value pattern signal is sent to the logical comparison circuit 600.
The reference clock signal, the test pattern signal and the period data signal (Rate signal) are input to the timing generator 200, and the timing generator 200 outputs a formatted clock signal and a comparative clock signal. The formatted clock signal is sent to the waveform formatter 500, and the comparative clock signal is sent to the logical comparison circuit 600.
The waveform formatter 500 formats the formatted clock signal into a waveform necessary for a test, and then sends a formatted pattern signal to a semiconductor device under test (hereinafter also abbreviated as “DUT” (device under test)) 700.
The logical comparison circuit 600 compares a response output of the DUT 700 with the expected value pattern signal on the basis of the comparative clock signal. Thus, whether the DUT 700 is good or bad is judged depending on whether the response output corresponds to the expected value pattern signal.
Next, the basic configuration of the timing generator is explained with reference to FIGS. 5 to 7.
FIGS. 5 and 6 show an example of a circuit for controlling a timing generator generally used at present and a variable delay circuit of the timing generator in real time. FIG. 5 shows a diagram of the whole configuration of the timing generator, and FIG. 6 shows a diagram of a detailed configuration of a multiplexer (MUX) and its periphery in the timing generator.
Moreover, FIG. 7 is a timing chart showing the operation of the timing generator.
As shown in FIG. 5, the timing generator 200 comprises a counter 210, first storage means (memory (U)) 220, second storage means (memory (L)) 230, a calibration data storage means (CAL Data) 240, a correspondence detection circuit 250, an adder 260, clock period delay means 270, a decoder 280 and a variable delay circuit 290 as shown, for example, in Japanese Patent Publication Laid-open No. 2001-235521 and Japanese Patent Publication Laid-open No. 8-94725.
Furthermore, as shown in FIG. 5, the variable delay circuit 290 includes a delay circuit 291 and a multiplexer (MUX) 292. As shown in FIG. 6, the delay circuit 291 has a plurality of cascaded clock buffers 293-1 to 293-n, and the MUX 292 comprises a plurality of AND circuits 294-0 to 294-n connected to the corresponding stages of the delay circuit 291, FIFOs 295-0 to 295-n respectively connected to the AND circuits 294-0 to 294-n, and an OR circuit 296 to which outputs of the plurality of AND circuits 294-0 to 294-n are input and which then outputs TG Out (a timing signal).
As shown in FIG. 7, a Refclk signal is input to the timing generator 200. It is to be noted that the period of the Refclk signal is 10 ns (FIG. 7(a)).
The output timing (test cycle TC) of a timing signal (TG Out, a delay clock in the semiconductor test apparatus 100) output from the timing generator 200 includes a point (TC1) 5 ns from a first start, and a point (TC2) 12 ns from a first start (after one period of the Refclk signal from the first start) (FIG. 7(b)).
A Rate signal indicating a start point is input to the timing generator 200 (FIG. 7(c)). In response to the input of the Rate signal, the counter 210 is cleared to 0 (FIG. 7(d)). Then, when the Rate signal is not input, the counter 210 is incremented one by one at each period of the Refclk signal (FIG. 7(d)).
The first storage means 220 stores a quotient when the test cycle (TC) of the output signal (TG Out) is divided by the period of the Refclk signal.
Furthermore, the second storage means 230 stores a remainder when the test cycle (TC) of the output signal (TG Out) is divided by the period of the Refclk signal.
For example, with regard to 5 ns which is the test cycle of the first output signal, the quotient and remainder are calculated using the following equation:5÷10=0 . . . 5  (Equation 1)
A quotient of 0 and a remainder of 5 ns are calculated by Equation 1. Based on the calculation results, the quotient “0” is stored in the first storage means 220, and the remainder “5 ns” is stored in the second storage means 230 (FIG. 7(e), (f)).
Moreover, with regard to 12 ns which is the test cycle of the second output signal, the quotient and remainder are calculated using the following equation:12÷10=1 . . . 2  (Equation 2)
A quotient of 1 and a remainder of 2 ns are calculated by Equation 2. Based on the calculation results, the quotient “1” is stored in the first storage means 220, and the remainder “2 ns” is stored in the second storage means 230 (FIG. 7(e), (f)).
Furthermore, the correspondence detection circuit 250 detects the correspondence between a counted value of the counter 210 and data stored in the first storage means 220. The correspondence detection circuit 250 outputs a detection signal when the two correspond to each other, but outputs no detection signal when the two do not correspond to each other.
For example, at the first cycle of the Refclk signal, the counted value corresponds to the stored data because the counter indicates “0” and the memory quotient is “0”. In this case, a detection signal is output (FIG. 7(g)).
Furthermore, for example, at the second cycle of the Refclk signal, the counted value does not correspond to the stored data because the counter indicates “0” and the memory quotient is “1”. In this case, no detection signal is output (FIG. 7(g)).
Then, for example, at the third cycle of the Refclk signal, the counted value corresponds to the stored data because the counter indicates “1” and the memory quotient is “1”. In this case, a detection signal is output (FIG. 7(g)).
In response to the detection signal from the correspondence detection circuit 250 and an addition result (Carry) from the adder 260, the clock period delay means 270 sends a delay amount signal (coarse resolution delay amount signal) whose resolution corresponds to one cycle of the Refclk signal to the variable delay circuit 290. In this manner, the position of the timing retrieved from the Refclk is shifted.
In accordance with the addition result in the adder 260 based on the data stored in the second storage means 230 and the CAL Data in the calibration data storage means 240, the decoder 280 sends a delay amount signal (fine resolution delay amount signal) whose resolution corresponds to a time less than one cycle of the Refclk signal to the variable delay circuit 290.
That is, the output signal of the decoder 280 is a signal for controlling “which stage number of the MUX to be output”, and the output signal of the clock period delay means 270 is a signal for controlling “whether to validate or invalidate the selection of the MUX” (Output Enable).
As shown in FIGS. 5 and 6, the delay circuit 291 of the variable delay circuit 290 has the plurality of cascaded clock buffers 293-1 to 293-n, and is divided into a plurality of stages so that the delay amount of each stage may be the same.
For example, if the delay amount of the whole delay circuit 291 is 10 ns and this delay circuit 291 is separated into ten stages, each stage has a delay amount of 1 ns. Then, if the MUX 292 divides the delay circuit 291 into ten stages, it is possible to provide the output signal (TG Out) with a delay of 0 ns at a zeroth stage, a delay of 1 ns at a first stage, a delay of 2 ns at a second stage, a delay of 3 ns at a third stage, and a delay of 9 ns at a ninth stage.
In addition, a clock (Clock (VD)) is input to the delay circuit 291, and the delay circuit 291 provides a predetermined delay amount to the clock at each stage and sends the result to the MUX 292.
As shown in FIG. 6, the AND circuits 294-0 to 294-n of the MUX 292 are provided to correspond to the respective stages of the delay circuit 291. For example, if the delay circuit 291 is separated into ten stages, the number of AND circuits 294-0 to 294-n provided is 9+1 (nine circuits corresponding to the zeroth stage to the ninth stage, and one circuit corresponding to the zeroth stage).
Furthermore, each of the AND circuits 294-0 to 294-n inputs the clock from the corresponding stage of the delay circuit 291 to one input terminal. For example, a clock provided with a delay amount (1 ns in the above-mentioned example) of one stage is input to the AND circuit 294-1 corresponding to the first stage. Further, a clock provided with a delay amount (2 ns in the above-mentioned example) of two stages is input to the AND circuit 294-2 corresponding to the second stage. Sill further, a clock provided with a delay amount (1×n [ns] in the above-mentioned example) of n stages is input to the AND circuit 294-n corresponding to the n-th stage. Further yet, a clock provided with a delay amount of zero stages (i.e., a clock with a delay amount of 0) is input to the AND circuit 294-0 corresponding to the zeroth stage.
Moreover, output signals of the FIFOs 295-0 to 295-n are input to the other input terminals of the AND circuits 294-0 to 294-n.
The FIFOs 295-0 to 295-n are connected to the corresponding stages of the delay circuit 291, in the same manner as the AND circuits 294-0 to 294-n. For example, if the delay circuit 291 is separated into ten stages, the number of FIFOs 295-0 to 295-n provided is 9+1 (nine FIFOs corresponding to the zeroth stage to the ninth stage, and one FIFO corresponding to the zeroth stage).
The delay amount signal (fine resolution delay amount signal) sent from the decoder 280 is input to the FIFOs 295-0 to 295-n. Then, the FIFOs 295-0 to 295-n output delay amount signals by a first-in first-out method on the basis of a clock (Clock (Logic)) and a clock (Clock (VD)), and send the delay amount signals to the AND circuits 294-0 to 294-n.
Here, the delay amount signal from the decoder 280 selects the FIFO 295-0 to 295-n and AND circuit 294-0 to 294-n to be operated. For example, when the output signal (TG Out) is output at the first test cycle (TC) shown in FIG. 7(b), a delay amount signal for operating the FIFO 295-5 and the AND circuit 294-5 corresponding to the fifth stage of the delay circuit 291 is output in order to provide a delay amount of 5 ns to the output signal (TG Out). Thus, the FIFO 295-5 and the AND circuit 294-5 alone are operated, and the output signal (TG Out) provided with a delay amount of 5 ns is output (FIG. 7(h)).
The output signals of the AND circuits 294-0 to 294-n are input to the OR circuit 296, and the OR circuit 296 outputs the output signal (TG Out) by OR.
Thus, the variable delay circuit 290 is a circuit for selecting a predetermined stage number of the cascaded circuit (the delay circuit 291) of the buffers 293-1 to 293-n to obtain a desired delay time for a timing signal (TG Out), wherein the writing of data is common in the respective stages but the timing of reading is different depending on the stage (the FIFOs 295-0 to 295-n are used).
That is, the timing generator 200 is capable of generating a desired delay time in an analog manner by the configuration described above.